A unified approach to constrained mapping and routing on network-on-chip architectures

• Published in: 2005 Third IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS'05) pp. 75 - 80
• Main Authors: Hansson, Andreas, Goossens, Kees, Rǎdulescu, Andrei
• Format: Conference Proceeding
• Language: English
• Published: New York, NY, USA ACM 19.09.2005; IEEE
• Series: ACM Conferences
• Subjects: Computer architecture; Decoding; Delay; Hardware > Communication hardware, interfaces and storage > Buses and high-speed links; Laboratories; mapping; Measurement; Network topology; Network-on-a-chip; network-on-chip; quality-of-service; Routing; Runtime; System-on-a-chip; system-on-chip; routing; mapping; network-on-chip; system-on-chip; quality-of-service
• ISBN: 9781595931610; 1595931619
• DOI: 10.1145/1084834.1084857

One of the key steps in Network-on-Chip (NoC) based design is spatial mapping of cores and routing of the communication between those cores. Known solutions to the mapping and routing problem first map cores onto a topology and then route communication, using separated and possibly conflicting objective functions. In this paper we present a unified single-objective algorithm, called Unified MApping, Routing and Slot allocation (UMARS). As the main contribution we show how to couple path selection, mapping of cores and TDMA time-slot allocation such that the network required to meet the constraints of the application is minimized. The time-complexity of UMARS is low and experimental results indicate a run-time only 20% higher than that of path selection alone. We apply the algorithm to an MPEG decoder System-on-Chip (SoC), reducing area by 33%, power by 35% and worst-case latency by a factor four over a traditional multi-step approach.