Universal fault simulation using fault tuples

We introduce a new fault representation mechanism for digital circuits based on fault tuples. A fault tuple is a simple 3-element condition for a signal line, its value, and clock cycle constrain t. AND-OR expressions of fault tuples are used to represent arbitrary misbehaviors. A fault simulator ba...

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Bibliographic Details
Published inProceedings 37th Design Automation Conference pp. 786 - 789
Main Authors Dwarakanath, Kumar N., Blanton, R. D.
Format Conference Proceeding
LanguageEnglish
Published New York, NY, USA ACM 01.01.2000
IEEE
SeriesACM Conferences
Subjects
Applied computing > Physical sciences and engineering > Engineering
Automatic test pattern generation
Clocks
Computer systems organization > Dependable and fault-tolerant systems and networks
Error correction
Fault detection
General and reference > Cross-computing tools and techniques > Performance
Hardware > Emerging technologies
Hardware > Robustness
Hardware > Very large scale integration design
Networks > Network performance evaluation
Performance evaluation
Testing
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Summary:We introduce a new fault representation mechanism for digital circuits based on fault tuples. A fault tuple is a simple 3-element condition for a signal line, its value, and clock cycle constrain t. AND-OR expressions of fault tuples are used to represent arbitrary misbehaviors. A fault simulator based on fault tuples was used to conduct experiments on benc hmark circuits. Simulation results show that a 17% reduction of average CPU time is achiev ed when performing sim ulation on all fault types simultaneously, as opposed to individually. We expect further improvements in speedup when the shared characteristics of the various fault types are better exploited.
ISBN:9781581131871
1581131879
DOI:10.1145/337292.337779