A new paradigm for synthesis and propagation of clock gating conditions

Clock gating has become a standard practice for saving dynamic power in the clock network. Due to design reuse, it is common to find designs that have already some partial clock gating. We propose to exploit the existing clock gating in order to extract stronger gating conditions for blocks that are...

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Bibliographic Details
Published in2008 45th ACM/IEEE Design Automation Conference pp. 658 - 663
Main Authors Fraer, Ranan, Kamhi, Gila, Mhameed, Muhammad K.
Format Conference Proceeding
LanguageEnglish
Published New York, NY, USA ACM 08.06.2008
IEEE
SeriesACM Conferences
Subjects
clock gating
Clocks
Design optimization
Energy consumption
Floating-point arithmetic
Hardware > Integrated circuits > Logic circuits
Logic design
Low-power design
Network synthesis
Pipelines
Power dissipation
Robust stability
Synchronization
clock gating
low-power design
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Summary:Clock gating has become a standard practice for saving dynamic power in the clock network. Due to design reuse, it is common to find designs that have already some partial clock gating. We propose to exploit the existing clock gating in order to extract stronger gating conditions for blocks that are poorly gated or not gated at all. A second contribution of our paper is a robust and scalable approach to extract stability conditions for clock gating. Finally, we present a uniform treatment of unobservability and stability as dual approaches for propagating gating conditions forward and backward. Experimental results demonstrate significant power reduction (in the range of 14% -- 55% of the clock power) on Intel micro-processor designs.
ISBN:1605581151
9781605581156
ISSN:0738-100X
DOI:10.1145/1391469.1391638