FASER Fast Analysis of Soft Error Susceptibility for Cell-Based Designs

• Published in: 7th International Symposium on Quality Electronic Design (ISQED'06) pp. 755 - 760
• Main Authors: Zhang, Bin, Wang, Wei-Shen, Orshansky, Michael
• Format: Conference Proceeding
• Language: English
• Published: Washington, DC, USA IEEE Computer Society 27.03.2006; IEEE
• Series: ACM Conferences
• Subjects: Bit error rate; Boolean functions; Circuit simulation; CMOS technology; Combinational circuits; Computational modeling; Data structures; Error analysis; Hardware > Hardware validation; Hardware > Hardware validation > Functional verification > Simulation and emulation; Hardware > Integrated circuits > Logic circuits; Hardware > Integrated circuits > Logic circuits > Finite state machines; Libraries; Single event upset
• ISBN: 9780769525235; 0769525237
• ISSN: 1948-3287; 1948-3295
• DOI: 10.1109/ISQED.2006.64

This paper is concerned with statically analyzing the susceptibility of arbitrary combinational circuits to single event upsets that are becoming a significant concern for reliability of commercial electronics. For the first time, a fast and accurate methodology FASER based on static, vector-less analysis of error rates due to single event upsets in general combinational circuits is proposed. Accurate models are based on STA-like pre-characterization methods, and logical masking is computed via binary decision diagrams with circuit partitioning. Experimental results indicate that FASER achieves good accuracy compared to the SPICE-based simulation method. The average error across the benchmark circuits is 12% at over 90,000X speed-up. The accuracy can be further improved by more accurate cell library characterization. The run-time for ISCAS'85 benchmark circuits ranges from 10 to 120 minutes. The estimated bit error rate (BER) for the ISCAS'85 benchmark circuits implemented in the 100nm CMOS technology is about 10-5 FIT.