Hierarchical memory size estimation for loop fusion and loop shifting in data-dominated applications

• Published in: Proceedings of the 2006 Asia and South Pacific Design Automation Conference pp. 606 - 611
• Main Authors: Hu, Qubo, Vandecappelle, Arnout, Palkovic, Martin, Kjeldsberg, Per Gunnar, Brockmeyer, Erik, Catthoor, Francky
• Format: Conference Proceeding
• Language: English
• Published: Piscataway, NJ, USA IEEE Press 01.01.2006
• Series: ACM Conferences
• Subjects: Hardware; Hardware > Hardware validation; Hardware > Integrated circuits > Semiconductor memory
• ISBN: 9780780394513; 0780394518
• DOI: 10.1145/1118299.1118442

Loop fusion and loop shifting are important transformations for improving data locality to reduce the number of costly accesses to off-chip memories. Since exploring the exact platform mapping for all the loop transformation alternatives is a time consuming process, heuristics steered by improved data locality are generally used. However, pure locality estimates do not sufficiently take into account the hierarchy of the memory platform. This paper presents a fast, incremental technique for hierarchical memory size requirement estimation for loop fusion and loop shifting at the early loop transformations design stage. As the exact memory platform is often not yet defined at this stage, we propose a platform-independent approach which reports the Pareto-optimal trade-off points for scratch-pad memory size and off-chip memory accesses. The estimation comes very close to the actual platform mapping. Experiments on realistic test-vehicles confirm that. It helps the designer or a tool to find the interesting loop transformations that should then be investigated in more depth afterward.