Quest for high-performance bufferless NoCs with single-cycle express paths and self-learning throttling

Router buffers are the main reason for the Network-on-Chip's (NoC) scalable bandwidth, but consumes significant area and power. The SCEPTER bufferless NoC sets up single-cycle virtual express paths dynamically, allowing packets to traverse non-minimal paths without latency penalty. Using priori...

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Bibliographic Details
Published in2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC) pp. 1 - 6
Main Authors Daya, Bhavya K., Li-Shiuan Peh, Chandrakasan, Anantha P.
Format Conference Proceeding
LanguageEnglish
Published IEEE 05.06.2016
Subjects
Pipelines
Ports (Computers)
Resource management
Routing
Routing protocols
Switches
Throughput
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Summary:Router buffers are the main reason for the Network-on-Chip's (NoC) scalable bandwidth, but consumes significant area and power. The SCEPTER bufferless NoC sets up single-cycle virtual express paths dynamically, allowing packets to traverse non-minimal paths without latency penalty. Using prioritization, bypassing, and throttling mechanisms, we maximize opportunities to use these paths while pushing bandwidth. For 64 and 256 nodes, we achieve 62% lower latency, 1.3× higher throughput, and 35% lower starvation over a baseline bufferless NoC for synthetic traffic. Full-system 36-core simulations show a 19% lower runtime, on-par performance to a buffered network, with 36% lower area, 33% lower power.
DOI:10.1145/2897937.2898075