Cross-layer racetrack memory design for ultra high density and low power consumption

The racetrack memory technology utilizes magnetic domains along a nanoscopic wire to obtain ultra-high data storage density. The recent success in the planar racetrack nanowire promised its fabrication feasibility and future scalability, bringing more design challenges and opportunities. In this pap...

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Bibliographic Details
Published in2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC) pp. 1 - 6
Main Authors Sun, Zhenyu, Wu, Wenqing, Li, Hai (Helen)
Format Conference Proceeding
LanguageEnglish
Published New York, NY, USA ACM 29.05.2013
IEEE
SeriesACM Conferences
Subjects
Arrays
Cross-layer design
Hardware > Integrated circuits > Semiconductor memory > Dynamic memory
Magnetic domains
Memory management
Microprocessors
Racetrack
Random access memory
Transistors
cross-layer design
racetrack
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Summary:The racetrack memory technology utilizes magnetic domains along a nanoscopic wire to obtain ultra-high data storage density. The recent success in the planar racetrack nanowire promised its fabrication feasibility and future scalability, bringing more design challenges and opportunities. In this paper, we initialize the optimization of racetrack memory embracing design considerations across multiple layers, including cell design, array structure, architecture organization, and data management. Our evaluation shows that racetrack memory based cache can achieve 6.4x area reduction, 25% performance enhancement, and 62% energy saving, compared to STT-RAM cache design. The benefit over SRAM technology is even more significant.
ISBN:1450320716
9781450320719
ISSN:0738-100X
DOI:10.1145/2463209.2488799