An efficient layout decomposition approach for triple patterning lithography

Triple Patterning Lithography (TPL) is widely recognized as a promising solution for 14/10nm technology node. In this paper, we propose an efficient layout decomposition approach for TPL, with the objective to minimize the number of conflicts and stitches. Based on our analysis of actual benchmarks,...

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Bibliographic Details
Published in2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC) pp. 1 - 6
Main Authors Kuang, Jian, Young, Evangeline F. Y.
Format Conference Proceeding
LanguageEnglish
Published New York, NY, USA ACM 29.05.2013
IEEE
SeriesACM Conferences
Subjects
Bridges
Color
Hardware > Electronic design automation > Physical design (EDA)
Law
Layout
Layout Decomposition
Libraries
Lithography
Manufacturability
Triple Patterning Lithography
triple patterning lithography
manufacturability
layout decomposition
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Summary:Triple Patterning Lithography (TPL) is widely recognized as a promising solution for 14/10nm technology node. In this paper, we propose an efficient layout decomposition approach for TPL, with the objective to minimize the number of conflicts and stitches. Based on our analysis of actual benchmarks, we found that the whole layout can be reduced into several types of small feature clusters, by some simplification methods, and the small clusters can be solved very efficiently. We also present a new stitch finding algorithm to find all possible legal stitch positions in TPL. Experimental results show that the proposed approach is very effective in practice, which can achieve significant reduction of manufacturing cost, compared to the previous work.
ISBN:1450320716
9781450320719
ISSN:0738-100X
DOI:10.1145/2463209.2488818