Reduced-order modeling of large linear subcircuits via a block Lanczos algorithm

• Published in: 32nd Design Automation Conference pp. 474 - 479
• Main Authors: Feldmann, P., Freund, R. W.
• Format: Conference Proceeding
• Language: English
• Published: New York, NY, USA ACM 01.01.1995
• Series: ACM Conferences
• Subjects: Admittance; Analytical models; Circuit analysis; Circuit simulation; Computational modeling; Computer networks; Ear; Hardware > Electronic design automation > Physical design (EDA); Hardware > Emerging technologies; Hardware > Integrated circuits > Interconnect; Hardware > Very large scale integration design; Linear circuits; Mathematics of computing > Mathematical analysis > Functional analysis > Approximation; Permission; Theory of computation > Design and analysis of algorithms > Approximation algorithms analysis; Transmission line matrix methods
• ISBN: 0897917251; 9780897917254
• ISSN: 0738-100X
• DOI: 10.1145/217474.217573

A method for the efficient computation of accurate reduced-order models of large linear circuits is described. The method, called MPVL, employs a novel block Lanczos algorithm to compute matrix Padé approximations of matrix-valued network transfer functions. The reduced-order models, computed to the required level of accuracy, are used to speed up the analysis of circuits containing large linear blocks. The linear blocks are replaced by their reduced-order models, and the resulting smaller circuit can be analyzed with general-purpose simulators, with significant savings in simulation time and, practically, no loss of accuracy.