A Formal Verification Method of Scheduling in High-level Synthesis

This paper describes a formal method for checking the equivalence between the finite state machine with data path (FSMD) model of the high-level behavioural specification and the FSMD model of the behaviour transformed by the scheduler. The method consists in introducing cutpoints in one FSMD, visua...

Full description

Saved in:
Bibliographic Details
Published in7th International Symposium on Quality Electronic Design (ISQED'06) pp. 71 - 78
Main Authors Karfa, C, Mandal, C, Sarkar, D, Pentakota, S R., Reade, Chris
Format Conference Proceeding
LanguageEnglish
Published Washington, DC, USA IEEE Computer Society 01.01.2006
IEEE
SeriesACM Conferences
Subjects
Online AccessGet full text

Cover

Loading…
More Information
Summary:This paper describes a formal method for checking the equivalence between the finite state machine with data path (FSMD) model of the high-level behavioural specification and the FSMD model of the behaviour transformed by the scheduler. The method consists in introducing cutpoints in one FSMD, visualizing its computations as concatenation of paths from cutpoints to cutpoints and finally, identifying equivalent finite path segments in the other FSMD; the process is then repeated with the FSMDs interchanged. The method is strong enough to accommodate merging of the segments in the original behaviour by the typical scheduler such as DLS, a feature very common in scheduling but not captured by many works reported in the literature. It also handles arithmetic transformations.
ISBN:9780769525235
0769525237
ISSN:1948-3287
1948-3295
DOI:10.1109/ISQED.2006.10