A new model for the high level description and simulation of VLSI networks

• Published in: 26th ACM/IEEE Design Automation Conference pp. 738 - 741
• Main Authors: van der Hoeven, A. J., de Lange, A. A., Deprettere, E. F., Dewilde, P. M.
• Format: Conference Proceeding
• Language: English
• Published: New York, NY, USA ACM 01.06.1989
• Series: ACM Conferences
• Subjects: Algorithm design and analysis; Computer languages; Computer systems organization > Architectures > Parallel architectures > Cellular architectures; Distributed computing; Hardware; Hardware > Electronic design automation > High-level and register-transfer level synthesis > Datapath optimization; Hardware > Electronic design automation > Logic synthesis > Circuit optimization; Hardware > Emerging technologies > Quantum technologies > Quantum dots and cellular automata; Hardware > Very large scale integration design; Hardware > Very large scale integration design > VLSI system specification and constraints; Machinery; Permission; Petri nets; Silicon compiler; Theory of computation > Models of computation; Very large scale integration; Writing
• ISBN: 0897913108; 9780897913102
• ISSN: 0738-100X
• DOI: 10.1145/74382.74517

A new applicative model is presented for the description and analysis of both synchronous and asynchronous VLSI networks at the top levels of abstraction. The model is based on two powerful paradigms, the Applicative State Transition concept of Backus [1] for the descriptive aspects and the theory of single token time(d) Petri Nets [2] [3] [4] for the communicative aspects of the model. These combined paradigms provide an elegant and fast method for the high level description and simulation of VLSI networks.