CPPC correctable parity protected cache

• Published in: 2011 38th Annual International Symposium on Computer Architecture (ISCA) pp. 223 - 234
• Main Authors: Manoochehri, Mehrtash, Annavaram, Murali, Dubois, Michel
• Format: Conference Proceeding
• Language: English
• Published: New York, NY, USA ACM 04.06.2011; IEEE
• Series: ACM Conferences
• Subjects: Arrays; Cache; Error correction; Error correction codes; Hardware > Integrated circuits > Semiconductor memory > Dynamic memory; Microprocessors; Parity; Program processors; Registers; Reliability; cache; parity; reliability
• ISBN: 9781450304726; 1450304729
• ISSN: 1063-6897; 2575-713X
• DOI: 10.1145/2000064.2000091

Due to shrinking feature sizes processors are becoming more vulnerable to soft errors. Write-back caches are particularly vulnerable since they hold dirty data that do not exist in other memory levels. While conventional error correcting codes can protect write-back caches, it has been shown that they are expensive in terms of area and power. This paper proposes a reliable write-back cache called Correctable Parity Protected Cache (CPPC) which adds error correction capability to a parity-protected cache. For this purpose, CPPC augments a write-back parity-protected cache with two registers: the first register stores the XOR of all data written to the cache and the second register stores the XOR of all dirty data that are removed from the cache. CPPC relies on parity to detect a fault and then on the two XOR registers to correct faults. By a novel combination of byte shifting and parity interleaving CPPC corrects both single and spatial multi-bit faults to provide a high degree of reliability. We compare CPPC with one-dimensional parity, SECDED (Single Error Correction Double Error Detection) and two-dimensional parity-protected caches. Our experimental results show that CPPC provides a high level of reliability while its overheads are less than the overheads of SECDED and two-dimensional parity.