Majority-Inverter Graph: A novel data-structure and algorithms for efficient logic optimization

• Published in: 2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC) pp. 1 - 6
• Main Authors: Amaru, Luca, Gaillardon, Pierre-Emmanuel, De Micheli, Giovanni
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.06.2014
• Subjects: Boolean Algebra; Boolean functions; DAG; Data structures; Delays; Inverters; Logic Synthesis; Majority Logic; Optimization; Switches
• ISSN: 0738-100X
• DOI: 10.1145/2593069.2593158

In this paper, we present Majority-Inverter Graph (MIG), a novel logic representation structure for efficient optimization of Boolean functions. An MIG is a directed acyclic graph consisting of three-input majority nodes and regular/complemented edges. We show that MIGs include any AND/OR/Inverter Graphs (AOIGs), containing also the wellknown AIGs. In order to support the natural manipulation of MIGs, we introduce a new Boolean algebra, based exclusively on majority and inverter operations, with a complete axiomatic system. Theoretical results show that it is possible to explore the entire MIG representation space by using only five primitive transformation rules. Such feature opens up a great opportunity for logic optimization and synthesis. We showcase the MIG potential by proposing a delay-oriented optimization technique. Experimental results over MCNC benchmarks show that MIG optimization reduces the number of logic levels by 18%, on average, with respect to AIG optimization performed by ABC academic tool. Employed in a traditional optimization-mapping circuit synthesis flow, MIG optimization enables an average reduction of {22%, 14%, 11%} in the estimated {delay, area, power} metrics, before physical design, as compared to academic/commercial synthesis flows.