Spectrum a hybrid nanophotonic-electric on-chip network

On many-core chip designs, short, often-multicast, latency-critical messages, used extensively in high-level coherence and synchronization protocols, often become the bottleneck of parallel performance scaling. This paper presents Spectrum, a hybrid nanophotonic-electric on-chip network that optimiz...

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Bibliographic Details
Published in2009 46th ACM/IEEE Design Automation Conference pp. 575 - 580
Main Authors Li, Zheng, Fay, Dan, Mickelson, Alan, Shang, Li, Vachharajani, Manish, Filipovic, Dejan, Park, Wounjhang, Sun, Yihe
Format Conference Proceeding
LanguageEnglish
Published New York, NY, USA ACM 26.07.2009
IEEE
SeriesACM Conferences
Subjects
Bandwidth
Broadcasting
Chip scale packaging
Coherence
Computer systems organization > Architectures > Parallel architectures > Interconnection architectures
Delay
Network-on-a-chip
Networks-on-Chip
optical communication
Planar waveguides
Protocols
silicon photonics
Throughput
Wavelength division multiplexing
silicon photonics
Networks-on-Chip
optical communication
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Summary:On many-core chip designs, short, often-multicast, latency-critical messages, used extensively in high-level coherence and synchronization protocols, often become the bottleneck of parallel performance scaling. This paper presents Spectrum, a hybrid nanophotonic-electric on-chip network that optimizes both throughput and latency. Spectrum's novel planar nanophotonic subnetwork broadcasts latency-critical messages through a wavelength-division multiplexed (WDM) two-dimensional waveguide. Spectrum's throughput-optimized packet-switching electrical subnetwork handles high bandwidth traffic. Overall, Spectrum delivers an almost ideal CMOS-compatible interconnection network for many-core systems.
ISBN:9781605584973
1605584975
ISSN:0738-100X
DOI:10.1145/1629911.1630060