PUFFER: A Routability-Driven Placement Framework via Cell Padding with Multiple Features and Strategy Exploration

• Published in: 2023 60th ACM/IEEE Design Automation Conference (DAC) pp. 1 - 6
• Main Authors: Cai, Zhijie, Zou, Peng, Wu, Zhengtao, Tong, Xingyu, Yu, Jun, Chen, Jianli, Chang, Yao-Wen
• Format: Conference Proceeding
• Language: English
• Published: IEEE 09.07.2023
• Subjects: Benchmark testing; cell padding; Graph neural networks; physical design; placement; Probabilistic logic; routability; Routing; Runtime; Semiconductor device manufacture; Very large scale integration
• DOI: 10.1109/DAC56929.2023.10247681

Placement is a critical stage in VLSI physical design, especially for routability optimization. Due to the large scale and high integration introduced by the advanced semiconductor manufacturing technology, there remains a significant challenge in routability in the placement stage, which will affect the subsequent routing process. This paper proposes a placement framework, called PUFFER, to optimize routability by cell padding and strategy exploration. The framework first estimates congestion by imitating the behaviors of routing detours and clustered cell spreading. Then it calculates cell padding based on multiple features inspired by the characteristics of convolutional and graph neural networks. Besides, it applies a Bayesian-based method to explore a better placement strategy. Compared with a commercial tool and the state-of-the-art academic RePlAce placer, experiments on industrial benchmarks show that our framework achieves the best routability on average, with a 2.7× speedup over the commercial tool.