Enabling parametric feasibility analysis in real-time calculus driven performance evaluation
This paper advocates a rigorously formal and compositional style for obtaining key performance and/or interface metrics of systems with real-time constraints. We propose a hierarchical approach that couples the independent and different by nature frameworks of Modular Performance Analysis with Real-...
Saved in:
Published in | 2011 Proceedings of the 14th International Conference on Compilers, Architectures and Synthesis for Embedded Systems (CASES) pp. 155 - 164 |
---|---|
Main Authors | , , , , , |
Format | Conference Proceeding |
Language | English |
Published |
New York, NY, USA
ACM
09.10.2011
IEEE |
Series | ACM Conferences |
Subjects | |
Online Access | Get full text |
Cover
Loading…
Abstract | This paper advocates a rigorously formal and compositional style for obtaining key performance and/or interface metrics of systems with real-time constraints. We propose a hierarchical approach that couples the independent and different by nature frameworks of Modular Performance Analysis with Real-time Calculus (MPA-RTC) and Parametric Feasibility Analysis (PFA). Recent work on Real-time Calculus (RTC) has established an embedding of state-based component models into RTC-driven performance analysis for dealing with more expressive component models. However, with the obtained analysis infrastructure it is possible to analyze components only for a fixed set of parameters, e.g., fixed CPU speeds, fixed buffer sizes etc., such that a big space of parameters remains unstudied. In this paper, we overcome this limitation by integrating the method of parametric feasibility analysis in an RTC-based modeling environment. Using the PFA tool-flow, we are able to find regions for component parameters that maintain feasibility and worst-case properties. As a result, the proposed analysis infrastructure produces a broader range of valid design candidates, and allows the designer to reason about the system robustness. |
---|---|
AbstractList | This paper advocates a rigorously formal and compositional style for obtaining key performance and/or interface metrics of systems with real-time constraints. We propose a hierarchical approach that couples the independent and different by nature frameworks of Modular Performance Analysis with Real-time Calculus (MPA-RTC) and Parametric Feasibility Analysis (PFA). Recent work on Real-time Calculus (RTC) has established an embedding of state-based component models into RTC-driven performance analysis for dealing with more expressive component models. However, with the obtained analysis infrastructure it is possible to analyze components only for a fixed set of parameters, e.g., fixed CPU speeds, fixed buffer sizes etc., such that a big space of parameters remains unstudied. In this paper, we overcome this limitation by integrating the method of parametric feasibility analysis in an RTC-based modeling environment. Using the PFA tool-flow, we are able to find regions for component parameters that maintain feasibility and worst-case properties. As a result, the proposed analysis infrastructure produces a broader range of valid design candidates, and allows the designer to reason about the system robustness. This paper advocates a rigorously formal and compositional style for obtaining key performance and/or interface metrics of systems with real-time constraints. We propose a hierarchical approach that couples the independent and different by nature frameworks of Modular Performance Analysis with Real-time Calculus (MPARTC) and Parametric Feasibility Analysis (PFA). Recent work on Real-time Calculus (RTC) has established an embedding of state-based component models into RTC-driven performance analysis for dealing with more expressive component models. However, with the obtained analysis infrastructure it is possible to analyze components only for a fixed set of parameters, e. g., fixed CPU speeds, fixed buffer sizes etc., such that a big space of parameters remains unstudied. In this paper, we overcome this limitation by integrating the method of parametric feasibility analysis in an RTC-based modeling environment. Using the PFA tool-flow, we are able to find regions for component parameters that maintain feasibility and worst-case properties. As a result, the proposed analysis infrastructure produces a broader range of valid design candidates, and allows the designer to reason about the system robustness. |
Author | Simalatsar, Alena Thiele, Lothar Ramadian, Yusi Lampka, Kai Perathoner, Simon Passerone, Roberto |
Author_xml | – sequence: 1 givenname: Alena surname: Simalatsar fullname: Simalatsar, Alena email: alena.simalatsar@epfl.ch organization: EPFL, Lausanne, Switzerland – sequence: 2 givenname: Yusi surname: Ramadian fullname: Ramadian, Yusi email: ramadian@disi.unitn.it organization: University of Trento, Trento, Italy – sequence: 3 givenname: Kai surname: Lampka fullname: Lampka, Kai email: Lampka@tik.ee.ethz.ch organization: ETHZ, Zurich, Switzerland – sequence: 4 givenname: Simon surname: Perathoner fullname: Perathoner, Simon email: perathoner@tik.ee.ethz.ch organization: ETHZ, Zurich, Switzerland – sequence: 5 givenname: Roberto surname: Passerone fullname: Passerone, Roberto email: roberto.passerone@unitn.it organization: University of Trento, Trento, Italy – sequence: 6 givenname: Lothar surname: Thiele fullname: Thiele, Lothar email: thiele@tik.ee.ethz.ch organization: ETHZ, Zurich, Switzerland |
BookMark | eNqNkL1PwzAQR40ACSidGVg8sqTYjuM4I6r4kiqxwIZknZMzMjhOZaeV-t-Tqp2YmH46Pb0b3hU5i0NEQm44W3Auq3vBSq0avdhvLcoTMm9qPQFWspqX7PTPfUHmOX8zxjifjFpcks_HCDb4-EXXkKDHMfmWOoTsrQ9-3FGIEHbZZ-ojTQihGH2PtIXQbsIm0y75LUa6xuSG1ENskeIWwgZGP8Rrcu4gZJwfd0Y-nh7fly_F6u35dfmwKkBoPRZWWl1JrbFTXYVSiVI60FKA0tZWSreOKbRWIpMgaqW41E3XuBpZo1zT1OWM3B7-ekQ06-R7SDujmBJM8okuDhTa3thh-MmGM7PPZ475zDGfscmjm4S7fwrlL1_db-M |
ContentType | Conference Proceeding |
Copyright | 2011 ACM |
Copyright_xml | – notice: 2011 ACM |
DBID | 6IE 6IL CBEJK RIE RIL |
DOI | 10.1145/2038698.2038723 |
DatabaseName | IEEE Electronic Library (IEL) Conference Proceedings IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume IEEE Xplore All Conference Proceedings IEEE Electronic Library (IEL) IEEE Proceedings Order Plans (POP All) 1998-Present |
DatabaseTitleList | |
Database_xml | – sequence: 1 dbid: RIE name: IEEE/IET Electronic Library (IEL) url: https://proxy.k.utb.cz/login?url=https://ieeexplore.ieee.org/ sourceTypes: Publisher |
DeliveryMethod | fulltext_linktorsrc |
Discipline | Engineering |
EISBN | 9781450307130 1450307132 |
EndPage | 164 |
ExternalDocumentID | 6062041 |
Genre | orig-research |
GroupedDBID | 6IE 6IF 6IK 6IL 6IN AAJGR ACM ADPZR ALMA_UNASSIGNED_HOLDINGS APO BEFXN BFFAM BGNUA BKEBE BPEOZ CBEJK GUFHI IEGSK IERZE OCL RIE RIL LHSKQ |
ID | FETCH-LOGICAL-a288t-b4b85488ed6d5e46234fa842a68bb568cf06ebb4e04a27661489d9f7e096f9973 |
IEDL.DBID | RIE |
ISBN | 9781450307130 1450307132 |
IngestDate | Wed Jun 26 19:27:42 EDT 2024 Wed Jan 31 06:42:55 EST 2024 |
IsDoiOpenAccess | false |
IsOpenAccess | true |
IsPeerReviewed | false |
IsScholarly | false |
Keywords | tool integration system-level design feasibility areas worst-case analysis |
Language | English |
License | Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from Permissions@acm.org |
LinkModel | DirectLink |
MeetingName | ESWeek '11: Seventh Embedded Systems Week |
MergedId | FETCHMERGED-LOGICAL-a288t-b4b85488ed6d5e46234fa842a68bb568cf06ebb4e04a27661489d9f7e096f9973 |
OpenAccessLink | http://disi.unitn.it/~roby/pdfs/SimalatsarRamadianPasseroneLampkaPerathonerThiele11CASES.pdf |
PageCount | 10 |
ParticipantIDs | acm_books_10_1145_2038698_2038723_brief ieee_primary_6062041 acm_books_10_1145_2038698_2038723 |
PublicationCentury | 2000 |
PublicationDate | 20111009 2011-Oct. |
PublicationDateYYYYMMDD | 2011-10-09 2011-10-01 |
PublicationDate_xml | – month: 10 year: 2011 text: 20111009 day: 09 |
PublicationDecade | 2010 |
PublicationPlace | New York, NY, USA |
PublicationPlace_xml | – name: New York, NY, USA |
PublicationSeriesTitle | ACM Conferences |
PublicationTitle | 2011 Proceedings of the 14th International Conference on Compilers, Architectures and Synthesis for Embedded Systems (CASES) |
PublicationTitleAbbrev | CASES |
PublicationYear | 2011 |
Publisher | ACM IEEE |
Publisher_xml | – name: ACM – name: IEEE |
SSID | ssj0001120372 |
Score | 1.5453738 |
Snippet | This paper advocates a rigorously formal and compositional style for obtaining key performance and/or interface metrics of systems with real-time constraints.... |
SourceID | ieee acm |
SourceType | Publisher |
StartPage | 155 |
SubjectTerms | Automata Clocks Computing methodologies -- Modeling and simulation -- Model development and analysis Computing methodologies -- Modeling and simulation -- Model development and analysis -- Model verification and validation Feasibility areas Gold Synchronization System-level Design Tool integration Worst-case Analysis |
Title | Enabling parametric feasibility analysis in real-time calculus driven performance evaluation |
URI | https://ieeexplore.ieee.org/document/6062041 |
hasFullText | 1 |
inHoldings | 1 |
isFullTextHit | |
isPrint | |
link | http://utb.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwjV1NS8NAEB1qT3rxoxXrFysIXtyabDab3bO0FKHSg4UehLCbbKCobWnTg_56Z5O0URH0toQlCTNL5s1k3huA69DiqWFCU5UpRXmSBVQj7qdCeE56JeVlHXL4KAZj_jAJJw243XJhrLVF85ntumXxLz-dJ2tXKrtDsM08x1LfkR4ruVp1PcVnXhCxSr3H5yGm9YEUyrVvBTIqxhHp5O3bEJUihvT3Ybh5etk68tJd56abfPwQZvzv6x1Au2brkdE2Dh1Cw86OYO-L0GALnnuOIoVLMtKuG8vJ8hNEf1Vv7DvZaJOQ6YwgjHylbuY8Qf-56uCKpEv3USSLmmVAapnwNoz7vaf7Aa3mKlDNpMyp4UZioiJtKtLQcgRAPNOSMy2kMaGQSeYJawy3HtcscgFcqlRlkcV0Bz0aBcfQnM1n9gQIE5HQCnf5mc81ptrMCKsijd5giZ9mHbhCo8cuYVjFJQc6jCvHxJVjOnDz557YLKcW79ZyVo8XpRBHXBn89PfLZ7DLNg17_jk08-XaXiCCyM1lcXQ-ATrqwIg |
link.rule.ids | 310,311,786,790,795,796,802,27956,55107 |
linkProvider | IEEE |
linkToHtml | http://utb.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwjV3PS8MwFA5jHtSLPzZx_owgeDGzTdM0OcvG1G3ssMEOQknaFIa6ja076F_vS9utKoLeQglteS_0fe_1fd9D6No3cGooV0QmUhIWJR5RgPsJ546VXolZXofs9XlnxB7H_riCbjdcGGNM1nxmmnaZ_cuPZ9HKlsruAGxTx7LUtyDOO0HO1iorKi51vIAW-j0u8yGx9wSXtoHLE0E2kEhFb9_GqGRRpL2Heuvn580jL81VqpvRxw9pxv--4D6ql3w9PNhEogNUMdNDtPtFarCGnluWJAVLPFC2H8sK82PAf0V37Dteq5PgyRQDkHwlduo8Bg_a-uASxwv7WcTzkmeAS6HwOhq1W8P7DikmKxBFhUiJZlpAqiJMzGPfMIBALFGCUcWF1j4XUeJwozUzDlM0sCFcyFgmgYGEB3waeEeoOp1NzTHClAdcSdjlJi5TkGxTzY0MFHiDRm6cNNAVGD20KcMyzFnQflg4Jiwc00A3f-4J9WJi4G41a_VwnktxhIXBT36_fIm2O8NeN-w-9J9O0Q5dt--5Z6iaLlbmHPBEqi-yY_QJjtXD3A |
openUrl | ctx_ver=Z39.88-2004&ctx_enc=info%3Aofi%2Fenc%3AUTF-8&rfr_id=info%3Asid%2Fsummon.serialssolutions.com&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=proceeding&rft.title=Proceedings+of+the+14th+international+conference+on+Compilers%2C+architectures+and+synthesis+for+embedded+systems&rft.atitle=Enabling+parametric+feasibility+analysis+in+real-time+calculus+driven+performance+evaluation&rft.au=Simalatsar%2C+Alena&rft.au=Ramadian%2C+Yusi&rft.au=Lampka%2C+Kai&rft.au=Perathoner%2C+Simon&rft.series=ACM+Conferences&rft.date=2011-10-09&rft.pub=ACM&rft.isbn=9781450307130&rft.spage=155&rft.epage=164&rft_id=info:doi/10.1145%2F2038698.2038723 |
thumbnail_l | http://covers-cdn.summon.serialssolutions.com/index.aspx?isbn=9781450307130/lc.gif&client=summon&freeimage=true |
thumbnail_m | http://covers-cdn.summon.serialssolutions.com/index.aspx?isbn=9781450307130/mc.gif&client=summon&freeimage=true |
thumbnail_s | http://covers-cdn.summon.serialssolutions.com/index.aspx?isbn=9781450307130/sc.gif&client=summon&freeimage=true |