Enabling parametric feasibility analysis in real-time calculus driven performance evaluation

• Published in: 2011 Proceedings of the 14th International Conference on Compilers, Architectures and Synthesis for Embedded Systems (CASES) pp. 155 - 164
• Main Authors: Simalatsar, Alena, Ramadian, Yusi, Lampka, Kai, Perathoner, Simon, Passerone, Roberto, Thiele, Lothar
• Format: Conference Proceeding
• Language: English
• Published: New York, NY, USA ACM 09.10.2011; IEEE
• Series: ACM Conferences
• Subjects: Automata; Clocks; Computing methodologies > Modeling and simulation > Model development and analysis; Computing methodologies > Modeling and simulation > Model development and analysis > Model verification and validation; Feasibility areas; Gold; Synchronization; System-level Design; Tool integration; Worst-case Analysis; tool integration; system-level design; feasibility areas; worst-case analysis
• ISBN: 9781450307130; 1450307132
• DOI: 10.1145/2038698.2038723

This paper advocates a rigorously formal and compositional style for obtaining key performance and/or interface metrics of systems with real-time constraints. We propose a hierarchical approach that couples the independent and different by nature frameworks of Modular Performance Analysis with Real-time Calculus (MPA-RTC) and Parametric Feasibility Analysis (PFA). Recent work on Real-time Calculus (RTC) has established an embedding of state-based component models into RTC-driven performance analysis for dealing with more expressive component models. However, with the obtained analysis infrastructure it is possible to analyze components only for a fixed set of parameters, e.g., fixed CPU speeds, fixed buffer sizes etc., such that a big space of parameters remains unstudied. In this paper, we overcome this limitation by integrating the method of parametric feasibility analysis in an RTC-based modeling environment. Using the PFA tool-flow, we are able to find regions for component parameters that maintain feasibility and worst-case properties. As a result, the proposed analysis infrastructure produces a broader range of valid design candidates, and allows the designer to reason about the system robustness.