A hybrid strategy for mapping multiple throughput-constrained applications on MPSoCs

• Published in: Proceedings of the 14th International Conference on Compilers, Architectures and Synthesis for Embedded Systems pp. 175 - 184
• Main Authors: Singh, Amit Kumar, Kumar, Akash, Srikanthan, Thambipillai
• Format: Conference Proceeding
• Language: English
• Published: New York, NY, USA ACM 09.10.2011; IEEE
• Series: ACM Conferences
• Subjects: Applied computing > Arts and humanities > Architecture (buildings) > Computer-aided design; Applied computing > Physical sciences and engineering > Engineering > Computer-aided design; Bandwidth; Computer systems organization > Embedded and cyber-physical systems; Computer systems organization > Real-time systems; Decoding; design-time analysis; Multiprocessor; Optimization; run-time mapping; Synchronous Dataflow; Throughput; Tiles; Timing; run-time mapping; synchronous dataflow; multiprocessor; throughput; design-time analysis
• ISBN: 9781450307130; 1450307132
• DOI: 10.1145/2038698.2038726

Modern embedded systems are based on Multiprocessor-Systems-on-Chip (MPSoCs) to meet the strict timing deadlines of multiple applications. MPSoC resources must be utilized efficiently by mapping the applications in throughput-aware manner in order to meet throughput constraints for each of them. A design-time methodology is applicable only to predefined set of applications with static behavior, which is incapable of handling dynamism in applications. On the other hand, a run-time approach can cater to the dynamism but cannot provide timing guarantees for all the applications due to large computation requirements at run-time. This paper presents a hybrid flow which performs compute intensive analysis at design-time to derive multiple resource-throughput trade-off points and selects one of these at run-time subject to available resources and desired throughput. Experimental results show that the design-time analysis is faster by 39%, provides better trade-off points and the run-time mapping is speeded up by 93% when compared to state-of-the-art techniques.