High-Performance FPGA-based Accelerator for Bayesian Neural Networks

• Published in: 2021 58th ACM/IEEE Design Automation Conference (DAC) pp. 1063 - 1068
• Main Authors: Fan, Hongxiang, Ferianc, Martin, Rodrigues, Miguel, Zhou, Hongyu, Niu, Xinyu, Luk, Wayne
• Format: Conference Proceeding
• Language: English
• Published: IEEE 05.12.2021
• Subjects: Artificial neural networks; Computer architecture; Energy efficiency; Hardware; Medical services; Monte Carlo methods; Uncertainty
• DOI: 10.1109/DAC18074.2021.9586137

Neural networks (NNs) have demonstrated their potential in a wide range of applications such as image recognition, decision making or recommendation systems. However, standard NNs are unable to capture their model uncertainty which is crucial for many safety-critical applications including healthcare and autonomous vehicles. In comparison, Bayesian neural networks (BNNs) are able to express uncertainty in their prediction via a mathematical grounding. Nevertheless, BNNs have not been as widely used in industrial practice, mainly because of their expensive computational cost and limited hardware performance. This work proposes a novel FPGA based hardware architecture to accelerate BNNs inferred through Monte Carlo Dropout. Compared with other state-of-the-art BNN accelerators, the proposed accelerator can achieve up to 4 times higher energy efficiency and 9 times better compute efficiency. Considering partial Bayesian inference, an automatic framework is proposed, which explores the trade-off between hardware and algorithmic performance. Extensive experiments are conducted to demonstrate that our proposed framework can effectively find the optimal points in the design space.