Designing a 2048-Chiplet, 14336-Core Waferscale Processor

Waferscale processor systems can provide the large number of cores, and memory bandwidth required by today's highly parallel workloads. One approach to building waferscale systems is to use a chiplet-based architecture where pre-tested chiplets are integrated on a passive silicon-interconnect w...

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Published in2021 58th ACM/IEEE Design Automation Conference (DAC) pp. 1183 - 1188
Main Authors Pal, Saptadeep, Liu, Jingyang, Alam, Irina, Cebry, Nicholas, Suhail, Haris, Bu, Shi, Iyer, Subramanian S., Pamarti, Sudhakar, Kumar, Rakesh, Gupta, Puneet
Format Conference Proceeding
LanguageEnglish
Published IEEE 05.12.2021
Subjects
Architecture
Buildings
Chiplet Assembly
Costs
Design automation
Fault tolerance
Fault tolerant systems
Memory management
Silicon Interconnect Fabric
Waferscale Processors
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DOI10.1109/DAC18074.2021.9586194

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Summary:Waferscale processor systems can provide the large number of cores, and memory bandwidth required by today's highly parallel workloads. One approach to building waferscale systems is to use a chiplet-based architecture where pre-tested chiplets are integrated on a passive silicon-interconnect wafer. This technology allows heterogeneous integration and can provide significant performance and cost benefits. However, designing such a system has several challenges such as power delivery, clock distribution, waferscale-network design, design for testability and fault-tolerance. In this work, we discuss these challenges and the solutions we employed to design a 2048-chiplet, 14,336-core waferscale processor system.
DOI:10.1109/DAC18074.2021.9586194