Formalized methodology for data reuse exploration in hierarchical memory mappings

Efficient use of an optimized memory hierarchy to exploit temporal locality in the memory accesses on array signals can have a very large impact on the power consumption in data dominated applications. In the past, this task has been identified as crucial in a complete low-power memory management me...

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Bibliographic Details
Published inProceedings of 1997 International Symposium on Low Power Electronics and Design pp. 30 - 35
Main Authors Diguet, J. Ph, Wuytack, S., Catthoor, F., De Man, H.
Format Conference Proceeding
LanguageEnglish
Published New York, NY, USA ACM 01.08.1997
IEEE
SeriesACM Conferences
Subjects
Cache storage
Costs
Energy consumption
Flow graphs
Frequency estimation
Hardware
Motion estimation
Permission
Runtime
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Summary:Efficient use of an optimized memory hierarchy to exploit temporal locality in the memory accesses on array signals can have a very large impact on the power consumption in data dominated applications. In the past, this task has been identified as crucial in a complete low-power memory management methodology. But effective formalized techniques to deal with this specific task have not been addressed yet. In this paper the design freedom available for the basic problem is explored in-depth and the outline of a systematic solution methodology is proposed. The efficiency of the methodology is illustrated on a real-life motion estimation application.
ISBN:9780897919036
0897919033
DOI:10.1145/263272.263278