Secure model checkers for Network-on-Chip (NoC) architectures
As chip multiprocessors (CMPs) are becoming more susceptible to process variation, crosstalk, and hard and soft errors, emerging threats from rogue employees in a compromised foundry are creating new vulnerabilities that could undermine the integrity of our chips with malicious alterations. As the N...
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Published in | 2016 International Great Lakes Symposium on VLSI (GLSVLSI) pp. 45 - 50 |
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Main Authors | , , |
Format | Conference Proceeding |
Language | English |
Published |
ACM
18.05.2016
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Subjects | |
Online Access | Get full text |
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Summary: | As chip multiprocessors (CMPs) are becoming more susceptible to process variation, crosstalk, and hard and soft errors, emerging threats from rogue employees in a compromised foundry are creating new vulnerabilities that could undermine the integrity of our chips with malicious alterations. As the Network-on-Chip (NoC) is a focal point of sensitive data transfer and critical device coordination, there is an urgent demand for secure and reliable communication. In this paper we propose Secure Model Checkers (SMCs), a real-time solution for control logic verification and functional correctness in the micro-architecture to detect Hardware Trojan (HT) induced denial-of-service attacks and improve reliability. In our evaluation, we show that SMCs provides significant security enhancements in real-time with only 1.5% power and 1.1% area overhead penalty in the micro-architecture. |
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DOI: | 10.1145/2902961.2903032 |