Secure model checkers for Network-on-Chip (NoC) architectures

As chip multiprocessors (CMPs) are becoming more susceptible to process variation, crosstalk, and hard and soft errors, emerging threats from rogue employees in a compromised foundry are creating new vulnerabilities that could undermine the integrity of our chips with malicious alterations. As the N...

Full description

Saved in:
Bibliographic Details
Published in2016 International Great Lakes Symposium on VLSI (GLSVLSI) pp. 45 - 50
Main Authors Boraten, Travis, DiTomaso, Dominic, Kodi, Avinash Karanth
Format Conference Proceeding
LanguageEnglish
Published ACM 18.05.2016
Subjects
Circuit faults
Computer crime
Fault tolerance
Fault tolerant systems
Hardware
Hardware security
Hardware trojan
Network-on-Chip
Online AccessGet full text

Cover

More Information
Summary:As chip multiprocessors (CMPs) are becoming more susceptible to process variation, crosstalk, and hard and soft errors, emerging threats from rogue employees in a compromised foundry are creating new vulnerabilities that could undermine the integrity of our chips with malicious alterations. As the Network-on-Chip (NoC) is a focal point of sensitive data transfer and critical device coordination, there is an urgent demand for secure and reliable communication. In this paper we propose Secure Model Checkers (SMCs), a real-time solution for control logic verification and functional correctness in the micro-architecture to detect Hardware Trojan (HT) induced denial-of-service attacks and improve reliability. In our evaluation, we show that SMCs provides significant security enhancements in real-time with only 1.5% power and 1.1% area overhead penalty in the micro-architecture.
DOI:10.1145/2902961.2903032