On reducing energy-consumption by late-inserting instructions into the issue queue

In the presence of a long-latency instruction as a L2 miss, the issue queue (IQ) may fill with instructions dependent on the L2 miss; consequently, the IQ will not expose instruction-level parallelism until resolving the miss. In the scope of memory-latency tolerant processors, we propose delaying t...

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Bibliographic Details
Published inProceedings of the 2007 international symposium on Low power electronics and design (ISLPED '07) pp. 371 - 374
Main Authors Morancho, E, Llabería, José María, Olivé, A
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.08.2007
Subjects
Buffer storage
Computer architecture
Degradation
Delay
Energy consumption
Energy resolution
L2 hit-miss prediction
memory-latency tolerant processors
Out of order
Parallel processing
Permission
Proposals
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Summary:In the presence of a long-latency instruction as a L2 miss, the issue queue (IQ) may fill with instructions dependent on the L2 miss; consequently, the IQ will not expose instruction-level parallelism until resolving the miss. In the scope of memory-latency tolerant processors, we propose delaying the insertion into the IQ of the instructions dependent on load instructions predicted to miss L2. These instructions will be stored in an instruction buffer instead of being inserted in the IQ. After resolving the L2 miss, the dependent instructions will be inserted into the IQ. Results show that the proposal reduces the total number of replays from 37% (integer benchs) to 61% (floating-point benchs), the average performance degradation is, at most, 2%, and the average overall-chip energy-consumption reduction is around 8% in FP benchs.
DOI:10.1145/1283780.1283861