Fair Queuing Memory Systems

• Published in: 2006 39th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO'06) pp. 208 - 222
• Main Authors: Nesbit, Kyle J., Aggarwal, Nidhi, Laudon, James, Smith, James E.
• Format: Conference Proceeding
• Language: English
• Published: Washington, DC, USA IEEE Computer Society 09.12.2006; IEEE
• Series: ACM Conferences
• Subjects: Bandwidth; Computer systems organization > Dependable and fault-tolerant systems and networks; Delay; General and reference > Cross-computing tools and techniques > Performance; Hardware > Hardware validation; High performance computing; Interference; Mathematics of computing > Probability and statistics > Statistical paradigms > Queueing theory; Networks > Network performance evaluation; Processor scheduling; Quality of service; Scheduling algorithm; Software and its engineering > Software organization and properties > Contextual software domains > Operating systems > Process management > Scheduling; System performance; Yarn
• ISBN: 0769527329; 9780769527321
• ISSN: 1072-4451
• DOI: 10.1109/MICRO.2006.24

We propose and evaluate a multi-thread memory scheduler that targets high performance CMPs. The proposed memory scheduler is based on concepts originally developed for network fair queuing scheduling algorithms. The memory scheduler is fair and provides Quality of Service (QoS) while improving system performance. On a four processor CMP running workloads containing a mix of applications with a range of memory bandwidth demands, the proposed memory scheduler provides QoS to all of the threads in all of the workloads, improves system performance by an average of 14% (41% in the best case), and reduces the variance in the threads' target memory bandwidth utilization from .2 to .0058.