NISQ+: Boosting quantum computing power by approximating quantum error correction

• Published in: 2020 ACM/IEEE 47th Annual International Symposium on Computer Architecture (ISCA) Vol. 2020; pp. 556 - 569
• Main Authors: Holmes, Adam, Jokar, Mohammad Reza, Pasandi, Ghasem, Ding, Yongshan, Pedram, Massoud, Chong, Frederic T.
• Format: Conference Proceeding Journal Article
• Language: English
• Published: United States IEEE 01.05.2020
• Subjects: Accuracy; Codes; Computer architecture; Computers; Decoding; Error correction; Logic gates; MATHEMATICS AND COMPUTING; Quantum computing; Quantum Error Correction; Quantum system; Qubit; Surface Code
• ISSN: 1063-6897; 2575-713X
• DOI: 10.1109/ISCA45697.2020.00053

Quantum computers are growing in size, and design decisions are being made now that attempt to squeeze more computation out of these machines. In this spirit, we design a method to boost the computational power of nearterm quantum computers by adapting protocols used in quantum error correction to implement "Approximate Quantum Error Correction (AQEC):" By approximating fully-fledged error correction mechanisms, we can increase the compute volume (qubits \times gates, or "Simple Quantum Volume (SQV)") of near-term machines. The crux of our design is a fast hardware decoder that can approximately decode detected error syndromes rapidly. Specifically, we demonstrate a proof-of-concept that approximate error decoding can be accomplished online in near-term quantum systems by designing and implementing a novel algorithm in superconducting Single Flux Quantum (SFQ) logic technology. This avoids a critical decoding backlog, hidden in all offline decoding schemes, that leads to idle time exponential in the number of T gates in a program [58].Our design utilizes one SFQ processing module per physical quantum bit. Employing state-of-the-art SFQ synthesis tools, we show that the circuit area, power, and latency are within the constraints of typical, contemporary quantum system designs. Under a pure dephasing error model, the proposed accelerator and AQEC solution is able to expand SQV by factors between 3,402 and 11,163 on expected near-term machines. The decoder achieves a 5% accuracy threshold as well as pseudo-thresholds of approximately 5%, 4.75%, 4.5%, and 3.5% physical error rates for code distances 3, 5, 7, and 9, respectively. Decoding solutions are achieved in a maximum of \sim20 nanoseconds on the largest code distances studied. By avoiding the exponential idle time in offline decoders, we achieve a 10x reduction in required code distances to achieve the same logical performance as alternative designs.