Managing power and performance for System-on-Chip designs using Voltage Islands

This paper discusses Voltage Islands, a system architecture and chip implementation methodology, that can be used to dramatically reduce active and static power consumption for System-on-Chip (SoC) designs. As technology scales for increased circuit density and performance, the need to reduce power...

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Published inDigest of technical papers - IEEE/ACM International Conference on Computer-Aided Design pp. 195 - 202
Main Authors Lackey, David E., Zuchowski, Paul S., Bednar, Thomas R., Stout, Douglas W., Gould, Scott W., Cohn, John M.
Format Conference Proceeding
LanguageEnglish
Published New York, NY, USA ACM 10.11.2002
IEEE
SeriesACM Conferences
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Abstract This paper discusses Voltage Islands, a system architecture and chip implementation methodology, that can be used to dramatically reduce active and static power consumption for System-on-Chip (SoC) designs. As technology scales for increased circuit density and performance, the need to reduce power consumption increases in significance as designers strive to utilize the advancing silicon capabilities. The consumer product market further drives the need to minimize chip power consumption.Effective use of Voltage Islands for meeting SoC power and performance requirements, while meeting Time to Market (TAT) demands, requires novel approaches throughout the design flow as well as special circuit components and chip powering structures. This paper outlines methods being used today to design Voltage Islands in a rapid-TAT product development environment, and discusses the need for industry EDA advances to create an industry-wide Voltage Island design capability.
AbstractList This paper discusses Voltage Islands, a system architecture and chip implementation methodology, that can be used to dramatically reduce active and static power consumption for System-on-Chip (SoC) designs. As technology scales for increased circuit density and performance, the need to reduce power consumption increases in significance as designers strive to utilize the advancing silicon capabilities. The consumer product market further drives the need to minimize chip power consumption.Effective use of Voltage Islands for meeting SoC power and performance requirements, while meeting Time to Market (TAT) demands, requires novel approaches throughout the design flow as well as special circuit components and chip powering structures. This paper outlines methods being used today to design Voltage Islands in a rapid-TAT product development environment, and discusses the need for industry EDA advances to create an industry-wide Voltage Island design capability.
Author Bednar, Thomas R.
Lackey, David E.
Gould, Scott W.
Cohn, John M.
Stout, Douglas W.
Zuchowski, Paul S.
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Keywords Performance evaluation
System architecture
Power consumption
Circuit design
Performance requirement
Integrated circuit
Product development
System on a chip
Computer aided design
Implementation
Language English
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SubjectTerms Applied sciences
Computer systems organization -- Architectures
Design. Technologies. Operation analysis. Testing
Electronics
Exact sciences and technology
Integrated circuits
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
Software and its engineering -- Software creation and management -- Software development process management -- Software development methods
Title Managing power and performance for System-on-Chip designs using Voltage Islands
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