Managing power and performance for System-on-Chip designs using Voltage Islands

This paper discusses Voltage Islands, a system architecture and chip implementation methodology, that can be used to dramatically reduce active and static power consumption for System-on-Chip (SoC) designs. As technology scales for increased circuit density and performance, the need to reduce power...

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Bibliographic Details
Published inDigest of technical papers - IEEE/ACM International Conference on Computer-Aided Design pp. 195 - 202
Main Authors Lackey, David E., Zuchowski, Paul S., Bednar, Thomas R., Stout, Douglas W., Gould, Scott W., Cohn, John M.
Format Conference Proceeding
LanguageEnglish
Published New York, NY, USA ACM 10.11.2002
IEEE
SeriesACM Conferences
Subjects
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Summary:This paper discusses Voltage Islands, a system architecture and chip implementation methodology, that can be used to dramatically reduce active and static power consumption for System-on-Chip (SoC) designs. As technology scales for increased circuit density and performance, the need to reduce power consumption increases in significance as designers strive to utilize the advancing silicon capabilities. The consumer product market further drives the need to minimize chip power consumption.Effective use of Voltage Islands for meeting SoC power and performance requirements, while meeting Time to Market (TAT) demands, requires novel approaches throughout the design flow as well as special circuit components and chip powering structures. This paper outlines methods being used today to design Voltage Islands in a rapid-TAT product development environment, and discusses the need for industry EDA advances to create an industry-wide Voltage Island design capability.
Bibliography:SourceType-Conference Papers & Proceedings-1
ObjectType-Conference Paper-1
content type line 25
ISBN:0780376072
9780780376076
ISSN:1092-3152
DOI:10.1145/774572.774601