Clock Period Minimization of Non-Zero Clock Skew Circuits

• Published in: International Conference on Computer Aided Design: Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design; 09-13 Nov. 2003 p. 809
• Main Authors: Huang, Shih-Hsu, Nieh, Yow-Tyng
• Format: Conference Proceeding
• Language: English
• Published: Washington, DC, USA IEEE Computer Society 09.11.2003
• Series: ACM Conferences
• Subjects: Hardware > Communication hardware, interfaces and storage > Buses and high-speed links; Hardware > Hardware validation; Hardware > Hardware validation > Functional verification > Simulation and emulation
• ISBN: 9781581137620; 1581137621
• ISSN: 1092-3152
• DOI: 10.5555/996070.1009979

It is known that the clock skew can be exploited as a manageableresource to improve the circuit performance. However, due to thelimitation of race condition, the optimal clock skew schedulingdoes not achieve the lower bound of the clock period. In thispaper, we propose a polynomial time complexity algorithm, whichincorporates optimal clock skew scheduling and delay insertion,for the synthesis of non-zero clock skew circuits. The mainadvantages of our algorithm include two parts. First, it guaranteesto achieve the lower bound of the clock period. Secondly, it alsotries to minimize the required inserted delays under the lowerbound of the clock period. Experimental data shows that, eventhough we only use the buffers in a standard cell library toimplement the delay insertion, our approach still works well.