Tier partitioning strategy to mitigate BEOL degradation and cost issues in monolithic 3D ICs

• Published in: 2016 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) pp. 1 - 7
• Main Authors: Samal, Sandeep Kumar, Nayak, Deepak, Ichihashi, Motoi, Banna, Srinivasa, Sung Kyu Lim
• Format: Conference Proceeding
• Language: English
• Published: ACM 01.11.2016
• Subjects: BEOL Degradation; Degradation; Integrated circuits; Monolithic 3D IC; Resistance; Three-dimensional displays; Tier-Aware Partitioning; Timing; Tungsten; Two dimensional displays
• ISSN: 1558-2434
• DOI: 10.1145/2966986.2967080

In this paper, we develop tier partitioning strategy to mitigate back-end-of-line (BEOL) interconnect delay degradation and cost issues in monolithic 3D ICs (M3D). First, we study the routing overhead and delay degradation caused by tungsten BEOL interconnect in the bottom-tier of M3D. Our study shows that tungsten BEOL reduces performance by up to 30% at 4× resistance increase of bottom-tier interconnect. In addition, the bottom-tier BEOL adds a routing overhead to 3D nets, which is neglected in the state-of-the-art flow. Next, we develop two partitioning methods targeted specifically towards BEOL impact reduction. Our path-based approach identifies critical timing paths and places their cells in the top-tier to reduce the impact of delay degradation and routing overhead. Our net-based partitioning methodology confines the nets with long 2D wirelength into the top-tier to reduce the overall routing demand, and hence the metal layer usage in the bottom-tier. This in turn results in BEOL cost savings. Using a foundry 22nm FDSOI technology and full-chip GDS designs, we achieve tolerance of up to 4× increase in the bottom-tier BEOL resistance using our partitioning strategy. In addition, we save up to 3 metal layers in the bottom-tier of our M3D designs with up to 32% power savings over 2D IC for an interconnect dominated benchmark.