A Content Aware Integer Register File Organization

• Published in: Proceedings of the 31st annual international symposium on Computer architecture p. 314
• Main Authors: Gonzalez, Gonzalez, Cristal, Adrian, Ortega, Daniel, Veidenbaum, Alexander, Valero, Mateo
• Format: Conference Proceeding
• Language: English
• Published: Washington, DC, USA IEEE Computer Society 02.03.2004
• Series: ACM Conferences
• Subjects: Applied sciences; Computer science; control theory; systems; Computer systems and distributed systems. User interface; Electronics; Exact sciences and technology; Integrated circuits; Integrated circuits by function (including memories and processors); Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Software; Energy consumption; Input output; Register file; Access time; Locality; Instruction level parallelism; Computer architecture; Superscalar processor; Clock; Energy savings; Optimization; 64 bit processor
• ISBN: 9780769521435; 0769521436
• DOI: 10.5555/998680.1006727

A register file is a critical component of a modernsuperscalar processor.It has a large number of entriesand read/write ports in order to enable high levels ofinstruction parallelism.As a result, the register file'sarea, access time, and energy consumption increasedramatically, significantly affecting the overallsuperscalar processor's performance and energyconsumption.This is especially true in 64-bitprocessors.This paper presents a new integer register fileorganization, which reduces energy consumption,area, and access time of the register file with a minimal effect on overall IPC.This is accomplished byexpoiting a new concept, partial value locality, whichis defined as occurence of mutiple live valueinstances identical in a subset of their bits.A possibleimplementation of the new register file is describedand shown to obtain proposed optimized register filedesigns.Overall, an energy reduction of over 50%, a18% decreas in area, and a 15% reduction in the accesstime are achieved in the new register file.Theenergy and area savings are achieved with a 1.7%reduction in IPC for integer applications and anegligible 0.3% in numerical applications, assumingthe same clock frequency.A performance increase ofup to 13% is possible if the clcok frequency can beincreases due to a reduction in the register file accesstime.This approach enables other, very promisingoptimizations, three of which are outlined in the paper.