SyFAxO-GeN Synthesizing FPGA-Based Approximate Operators with Generative Networks

• Published in: 2023 28th Asia and South Pacific Design Automation Conference (ASP-DAC) pp. 402 - 409
• Main Authors: Ranjan, Rohit, Ullah, Salim, Sahoo, Siva Satyendra, Kumar, Akash
• Format: Conference Proceeding
• Language: English
• Published: New York, NY, USA ACM 16.01.2023
• Series: ACM Conferences
• Subjects: AI-based Exploration; Approximate Computing; Arithmetic Operator Design; Asia; Circuit Synthesis; Computer architecture; Computer systems organization; Computer systems organization > Architectures; Computer systems organization > Architectures > Other architectures; Computer systems organization > Architectures > Other architectures > Neural networks; Computing methodologies; Computing methodologies > Machine learning; Computing methodologies > Machine learning > Machine learning approaches; Computing methodologies > Machine learning > Machine learning approaches > Learning latent representations; Degradation; Design automation; Generative adversarial networks; Hardware; Hardware > Electronic design automation; Hardware > Electronic design automation > Logic synthesis; Hardware > Electronic design automation > Logic synthesis > Combinational synthesis; Hardware > Integrated circuits; Hardware > Integrated circuits > Reconfigurable logic and FPGAs; Hardware > Integrated circuits > Reconfigurable logic and FPGAs > Hardware accelerators; Hardware > Integrated circuits > Reconfigurable logic and FPGAs > Programmable logic elements; Hardware > Integrated circuits > Reconfigurable logic and FPGAs > Reconfigurable logic applications; Privacy; Training; AI-based exploration; arithmetic operator design; approximate computing; circuit synthesis
• ISBN: 9781450397834; 1450397832
• ISSN: 2153-697X
• DOI: 10.1145/3566097.3567891

With rising trends of moving AI inference to the edge, due to communication and privacy challenges, there has been a growing focus on designing low-cost Edge-AI. Given the diversity of application areas at the edge, FPGA-based systems are increasingly used for high-performance inference. Similarly, approximate computing has emerged as a viable approach to achieve disproportionate resource gains by utilizing the applications' inherent robustness. However, most related research has focused on selecting the appropriate approximate operators for an application from a set of ASIC-based designs. This approach fails to leverage the FPGA's architectural benefits and limits the scope of approximation to already existing generic designs. To this end, we propose an AI-based approach to synthesizing novel approximate operators for FPGA's Look-up-table-based structure. Specifically, we use state-of-the-art generative networks to search for constraint-aware arithmetic operator designs optimized for FPGA-based implementation. With the proposed GANs, we report up to 49% faster training, with negligible accuracy degradation, than related generative networks. Similarly, we report improved hypervolume and increased pareto-front design points compared to state-of-the-art approaches to synthesizing approximate multipliers.