Layout aware line-edge roughness modeling and poly optimization for leakage minimization

Line-edge roughness (LER) highly affects the device saturation current and leakage current, which leads to serious device performance degradation. In this paper, we propose the first layout-aware LER model where LER is highly related to the lithographic aerial image fidelity and neighboring geometri...

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Bibliographic Details
Published in2011 48th ACM/EDAC/IEEE Design Automation Conference (DAC) pp. 447 - 452
Main Authors Ban, Yongchan, Yang, Jae-Seok
Format Conference Proceeding
LanguageEnglish
Published New York, NY, USA ACM 05.06.2011
IEEE
SeriesACM Conferences
Subjects
Hardware > Electronic design automation > Physical design (EDA)
Layout
Leakage
Leakage current
Line-edge roughness
Lithography
Logic gates
Optimization
Performance evaluation
Transistors
lithography
optimization
leakage
line-edge roughness
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Summary:Line-edge roughness (LER) highly affects the device saturation current and leakage current, which leads to serious device performance degradation. In this paper, we propose the first layout-aware LER model where LER is highly related to the lithographic aerial image fidelity and neighboring geometric proximity. With our new LER model, we perform robust LER aware poly layout optimization to minimize the degradation of device performance, in particular leakage current. The results on 32nm node standard cells show average 91.26% reduction of leakage current and 4.46% improvement of saturation current at the worst case despite 8.86% area penalty.
ISBN:1450306365
9781450306362
ISSN:0738-100X
DOI:10.1145/2024724.2024828