Exploiting die-to-die thermal coupling in 3D IC placement

In this paper, we propose two methods used in 3D IC placement that effectively exploit the die-to-die thermal coupling in the stack. First, TSVs are spread on each die to reduce the local power density and vertically aligned across dies simultaneously to increase thermal conductivity to the heatsink...

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Bibliographic Details
Published inDAC Design Automation Conference 2012 pp. 741 - 746
Main Authors Athikulwongse, Krit, Pathak, Mohit, Lim, Sung Kyu
Format Conference Proceeding
LanguageEnglish
Published New York, NY, USA ACM 03.06.2012
IEEE
SeriesACM Conferences
Subjects
3D IC
Conductivity
Force
Hardware > Electronic design automation > Physical design (EDA) > Placement
Hardware > Electronic design automation > Physical design (EDA) > Wire routing
Heating
Springs
Temperature
Thermal conductivity
Thermal force
Through-silicon vias
TSV
temperature
TSV
3D IC
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Summary:In this paper, we propose two methods used in 3D IC placement that effectively exploit the die-to-die thermal coupling in the stack. First, TSVs are spread on each die to reduce the local power density and vertically aligned across dies simultaneously to increase thermal conductivity to the heatsink. Second, we move high-power logic cells to the location that has higher conductivity to the heatsink while moving TSVs in the upper dies so that high-power cells are vertically overlapping below the TSVs. These methods are employed in a force-directed 3D placement successfully and outperform several state-of-the-art placers published in recent literature.
ISBN:1450311997
9781450311991
ISSN:0738-100X
DOI:10.1145/2228360.2228495