VeriTrust verification for hardware trust
Hardware Trojans (HTs) implemented by adversaries serve as backdoors to subvert or augment the normal operation of infected devices, which may lead to functionality changes, sensitive information leakages, or Denial of Service attacks. To tackle such threats, this paper proposes a novel verification...
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Published in | 2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC) pp. 1 - 8 |
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Main Authors | , , , , |
Format | Conference Proceeding |
Language | English |
Published |
New York, NY, USA
ACM
29.05.2013
IEEE |
Series | ACM Conferences |
Subjects | |
Online Access | Get full text |
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Summary: | Hardware Trojans (HTs) implemented by adversaries serve as backdoors to subvert or augment the normal operation of infected devices, which may lead to functionality changes, sensitive information leakages, or Denial of Service attacks. To tackle such threats, this paper proposes a novel verification technique for hardware trust, namely VeriTrust, which facilitates to detect HTs inserted at design stage. Based on the observation that HTs are usually activated by dedicated trigger inputs that are not sensitized with verification test cases, VeriTrust automatically identifies such potential HT trigger inputs by examining verification corners. The key difference between VeriTrust and existing HT detection techniques is that VeriTrust is insensitive to the implementation style of HTs. Experimental results show that VeriTrust is able to detect all HTs evaluated in this paper (constructed based on various HT design methodologies shown in the literature) at the cost of moderate extra verification time, which is not possible with existing solutions. |
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ISBN: | 1450320716 9781450320719 |
ISSN: | 0738-100X |
DOI: | 10.1145/2463209.2488808 |