Memory partitioning for multidimensional arrays in high-level synthesis

• Published in: 2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC) pp. 1 - 8
• Main Authors: Wang, Yuxin, Li, Peng, Zhang, Peng, Zhang, Chen, Cong, Jason
• Format: Conference Proceeding
• Language: English
• Published: New York, NY, USA ACM 29.05.2013; IEEE
• Series: ACM Conferences
• Subjects: Algorithm design and analysis; Arrays; Benchmark testing; Hardware > Electronic design automation > High-level and register-transfer level synthesis; High-Level Synthesis; Memory management; Memory Padding; Memory Partitioning; Partitioning algorithms; Random access memory; Vectors; high-level synthesis; memory padding; memory partitioning
• ISBN: 1450320716; 9781450320719
• ISSN: 0738-100X
• DOI: 10.1145/2463209.2488748

Memory partitioning is widely adopted to efficiently increase the memory bandwidth by using multiple memory banks and reducing data access conflict. Previous methods for memory partitioning mainly focused on one-dimensional arrays. As a consequence, designers must flatten a multidimensional array to fit those methodologies. In this work we propose an automatic memory partitioning scheme for multidimensional arrays based on linear transformation to provide high data throughput of on-chip memories for the loop pipelining in high-level synthesis. An optimal solution based on Ehrhart points counting is presented, and a heuristic solution based on memory padding is proposed to achieve a near optimal solution with a small logic overhead. Compared to the previous one-dimensional partitioning work, the experimental results show that our approach saves up to 21% of block RAMs, 19% in slices, and 46% in DSPs.