BMF-BD: Bayesian model fusion on Bernoulli distribution for efficient yield estimation of integrated circuits

• Published in: 2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC) pp. 1 - 6
• Main Authors: Chenlei Fang, Fan Yang, Xuan Zeng, Xin Li
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.06.2014
• Subjects: Accuracy; Bayes methods; Integrated circuit modeling; Maximum likelihood estimation; Silicon; Yield estimation
• ISSN: 0738-100X
• DOI: 10.1145/2593069.2593099

Accurate yield estimation is one of the important yet challenging tasks for both pre-silicon verification and post-silicon validation. In this paper, we propose a novel method of Bayesian model fusion on Bernoulli distribution (BMF-BD) for efficient yield estimation at the late stage by borrowing the prior knowledge from an early stage. BMF-BD is particularly developed to handle the cases where the pre-silicon simulation and/or post-silicon measurement results are binary: either "pass" or "fail". The key idea is to model the binary simulation/measurement outcome as a Bernoulli distribution and then encode the prior knowledge as a Beta distribution based on the theory of conjugate prior. As such, the late-stage yield can be accurately estimated through Bayesian inference with very few late-stage samples. Several circuit examples demonstrate that BMF-BD achieves up to 10× cost reduction over the conventional estimator without surrendering any accuracy.