Efficient multiple-bit retention register assignment for power gated design concept and algorithms

• Published in: 2012 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) pp. 309 - 316
• Main Authors: Chen, Yu-Guang, Shi, Yiyu, Lai, Kuan-Yu, Hui, Geng, Chang, Shih-Chieh
• Format: Conference Proceeding
• Language: English
• Published: New York, NY, USA ACM 05.11.2012; IEEE
• Series: ACM Conferences
• Subjects: Algorithm design and analysis; Applied computing > Arts and humanities > Architecture (buildings) > Computer-aided design; Applied computing > Physical sciences and engineering > Engineering > Computer-aided design; Clocks; Flip-flops; Hardware > Hardware validation; Hardware > Integrated circuits; Latches; Low power; power gating; Registers; retention register; Synchronization; Transistors; power gating; low power; retention register
• ISBN: 9781450315739; 1450315739
• ISSN: 1092-3152
• DOI: 10.1145/2429384.2429448

Retention registers have been widely used in power gated design to store data during sleep mode. Since they consume much larger area and power than normal registers, it is imperative to minimize the total retention storage size. The current industry practice only replace all registers with single-bit retention ones, which significantly limits the design freedom and results in excessive area and power overhead. Towards this, for the first time in literature, we propose the concept of multi-bit retention register, with which only selected registers need to be replaced. It can significantly reduce the number of bits that need to be stored and thus the area and leakage power, but needs several clock cycles for mode transition. In addition, an efficient assignment algorithm is developed to minimize the total retention storage size subject to mode transition latency constraint. Experimental results show that our framework on average can reduce the leakage power in sleep mode and the retention storage area by 66.03%, compared with the single-bit retention register based design.