Runtime dependency analysis for loop pipelining in high-level synthesis

Research on High-Level Synthesis has mainly focused on applications with statically determinable characteristics and current tools often perform poorly in presence of data-dependent memory accesses. The reason is that they rely on conservative static scheduling strategies, which lead to inefficient...

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Bibliographic Details
Published in2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC) pp. 1 - 10
Main Authors Alle, Mythri, Morvan, Antoine, Derrien, Steven
Format Conference Proceeding
LanguageEnglish
Published New York, NY, USA ACM 29.05.2013
IEEE
SeriesACM Conferences
Subjects
Arrays
Hardware
Hardware > Electronic design automation > High-level and register-transfer level synthesis
Hardware > Electronic design automation > Physical design (EDA)
Hardware > Emerging technologies
Hardware > Very large scale integration design
Kernel
Pipeline processing
Runtime
Schedules
Shift registers
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Summary:Research on High-Level Synthesis has mainly focused on applications with statically determinable characteristics and current tools often perform poorly in presence of data-dependent memory accesses. The reason is that they rely on conservative static scheduling strategies, which lead to inefficient implementations. In this work, we propose to address this issue by leveraging well-known techniques used in superscalar processors to perform runtime memory disambiguation. Our approach, implemented as a source-to-source transformation at the C level, demonstrates significant performance improvements for a moderate increase in area while retaining portability among HLS tools.
ISBN:1450320716
9781450320719
ISSN:0738-100X
DOI:10.1145/2463209.2488796