Configurable analog routing methodology via technology and design constraint unification

In this paper, we present a novel configurable analog routing methodology for more efficient analog layout automation. By the help of OpenAccess constraint group format, the technology process rules and analog layout design intention/constraints are unified through schematic level to layout level. I...

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Bibliographic Details
Published in2012 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) pp. 620 - 626
Main Authors Pan, Po-Cheng, Chen, Hung-Ming, Cheng, Yi-Kan, Liu, Jill, Hu, Wei-Yi
Format Conference Proceeding
LanguageEnglish
Published New York, NY, USA ACM 05.11.2012
IEEE
SeriesACM Conferences
Subjects
Algorithm design and analysis
Applied computing > Arts and humanities > Architecture (buildings) > Computer-aided design
Applied computing > Physical sciences and engineering > Engineering > Computer-aided design
Foundries
Guidelines
Hardware > Electronic design automation > Physical design (EDA) > Placement
Hardware > Electronic design automation > Physical design (EDA) > Wire routing
Hardware > Robustness
Layout
Routing
Semantics
Topology
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Summary:In this paper, we present a novel configurable analog routing methodology for more efficient analog layout automation. By the help of OpenAccess constraint group format, the technology process rules and analog layout design intention/constraints are unified through schematic level to layout level. In contrast to self-defined constraint format in prior arts, proposed approach manipulates the analog routing characteristic based on the unified constraints. In different circuit hierarchies defined by circuit designers or extracted by existing placement, the hierarchical structure is formed as specific analog layout constraint groups. This work efficiently facilitates analog routing strategy which honors the specific analog constraints. By practicing on an analog functional block of tsmc 40nm SoC design which guarantees to be legalized and satisfies required analog constraints by DRC/LVS and post-layout simulation respectively, the results in wire matching for signal integrity show that the different routing priority generated by our approach can have significant performance impact.
ISBN:9781450315739
1450315739
ISSN:1092-3152
1558-2434
DOI:10.1145/2429384.2429517