A 25-dBm 1-GHz power amplifier integrated in CMOS 180nm for wireless power transferring

This paper presents the design of a power amplifier integrated in a CMOS 180 nm technology, which is intended to drive an inductive link operating at 990 MHz. A class-D topology is employed to avoid the use of inductors. A design methodology is proposed to find the optimal transistor width, solving...

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Bibliographic Details
Published in2015 28th Symposium on Integrated Circuits and Systems Design (SBCCI) pp. 1 - 6
Main Authors Cabrera, Fabian L., Rangel de Sousa, F.
Format Conference Proceeding
LanguageEnglish
Published ACM 01.08.2015
Subjects
Capacitance
Capacitors
Class-D
CMOS
CMOS integrated circuits
Impedance
Inductors
integrated circuits
Logic gates
power amplifier
power efficiency
Transistors
wireless power transfer
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Summary:This paper presents the design of a power amplifier integrated in a CMOS 180 nm technology, which is intended to drive an inductive link operating at 990 MHz. A class-D topology is employed to avoid the use of inductors. A design methodology is proposed to find the optimal transistor width, solving the trade-off between the ON-resistance and gate capacitance. The area occupied is 1.5 mm2, most of it is used by the PADs and the wide interconnects. Post-layout simulations showed a power efficiency of 58% when delivering 25.1 dBm to the primary inductor of a wireless power transferring system.
DOI:10.1145/2800986.2800989