Energy estimation and optimization of embedded VLIW processors based on instruction clustering

• Published in: Annual ACM IEEE Design Automation Conference: Proceedings of the 39th conference on Design automation : New Orleans, Louisiana, USA; 10-14 June 2002 pp. 886 - 891
• Main Authors: Bona, A., Sami, M., Sciuto, D., Zaccaria, V., Silvano, C., Zafalon, R.
• Format: Conference Proceeding
• Language: English
• Published: New York, NY, USA ACM 10.06.2002
• Series: ACM Conferences
• Subjects: Applied sciences; Electronics; Exact sciences and technology; Hardware > Integrated circuits; Hardware > Integrated circuits > Logic circuits; Integrated circuits; Integrated circuits by function (including memories and processors); Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; vliw architectures; power estimation; Very long instruction word processor; Very long instruction word; Instruction level parallelism
• ISBN: 1581134614; 9781581134612
• ISSN: 0738-100X
• DOI: 10.1145/513918.514137

Aim of this paper is to propose a methodology for the definition of an instruction-level energy estimation framework for VLIW (Very Long Instruction Word) processors. The power modeling methodology is the key issue to define an effective energy-aware software optimisation strategy for state-of-the-art ILP (Instruction Level Parallelism) processors. The methodology is based on an energy model for VLIW processors that exploits instruction clustering to achieve an efficient and fine grained energy estimation. The approach aims at reducing the complexity of the characterization problem for VLIW processors from exponential, with respect to the number of parallel operations in the same very long instruction, to quadratic, with respect to the number of instruction clusters. Furthermore, the paper proposes a spatial scheduling algorithm based on a low-power reordering of the parallel operations within the same long instruction. Experimental results have been carried out on the Lx processor, a 4-issue VLIW core jointly designed by HPLabs and STMicroelectronics. The results have shown an average error of 1.9% between the cluster-based estimation model and the reference design, with a standard deviation of 5.8%. For the Lx architecture, the spatial instruction scheduling algorithm provides an average energy saving of 12%.