The Statistics of Device Variations and its Impact on SRAM Bitcell Performance, Leakage and Stability

It has been recognized that as CMOS technology scales, the accompanied scaling of the conventional 6T-SRAM bitcell will require careful assessment of the role of device variations on its stability, electrical performance and leakage. As part of our SRAM design methodology, we have studied the statis...

Full description

Saved in:
Bibliographic Details
Published in7th International Symposium on Quality Electronic Design (ISQED'06) pp. 190 - 195
Main Authors Venkatraman, R., Castagnetti, R., Ramesh, S.
Format Conference Proceeding
LanguageEnglish
Published Washington, DC, USA IEEE Computer Society 27.03.2006
IEEE
SeriesACM Conferences
Subjects
CMOS logic circuits
CMOS technology
Condition monitoring
Hardware > Hardware validation
Hardware > Integrated circuits > Semiconductor memory
Hardware > Integrated circuits > Semiconductor memory > Static memory
Large scale integration
Logic devices
Random access memory
Robustness
Stability
Statistics
Testing
Online AccessGet full text

Cover

More Information
Summary:It has been recognized that as CMOS technology scales, the accompanied scaling of the conventional 6T-SRAM bitcell will require careful assessment of the role of device variations on its stability, electrical performance and leakage. As part of our SRAM design methodology, we have studied the statistics of local and across-wafer variations in bitcell-related parameters by using a series of specialized electrical test structures. The resulting quantification of the device variations are useful towards developing accurate mismatch models that can in turn be used to design not only robust SRAM bitcells but also functionally robust memory arrays wherein the role of bitline leakage and the statistics of 'tail-bits' are
ISBN:9780769525235
0769525237
ISSN:1948-3287
1948-3295
DOI:10.1109/ISQED.2006.134