Time Redundancy Based Scan Flip-Flop Reuse To Reduce SER Of Combinational Logic

• Published in: 7th International Symposium on Quality Electronic Design (ISQED'06) pp. 617 - 624
• Main Authors: Elakkumanan, Praveen, Prasad, Kishan, Sridhar, Ramalingam
• Format: Conference Proceeding
• Language: English
• Published: Washington, DC, USA IEEE Computer Society 27.03.2006; IEEE
• Series: ACM Conferences
• Subjects: Circuit simulation; Clocks; Flip-flops; Frequency; Hardware > Hardware test; Hardware > Hardware validation; Hardware > Hardware validation > Functional verification > Simulation and emulation; Hardware > Integrated circuits > Logic circuits > Combinational circuits; Hardware > Robustness; Latches; Logic; Neutrons; Redundancy; Single event transient; Voltage
• ISBN: 9780769525235; 0769525237
• ISSN: 1948-3287; 1948-3295
• DOI: 10.1109/ISQED.2006.137

With technology scaling, combinational logic is becoming increasingly vulnerable to radiation strikes. Classical fault tolerant techniques mainly address Single Even Upsets (SEUs). Robust combinational logic designs capable of tolerating Single Event Transients (SETs) also are needed in lower technology nodes. In this paper, we present a novel SET mitigation scheme for flip-flops based on the time redundancy principle. The incurred area overhead due to the radiation hardening is minimized by reusing existing components (uses existing scan portion for SET tolerance). As shown by the simulation results, the proposed SET tolerant flip-flop has no performance overheads and simulation results that show the area overheads in ISCAS benchmark circuits are also presented.