Combined BEM/FEM substrate resistance modeling

• Published in: Annual ACM IEEE Design Automation Conference: Proceedings of the 39th conference on Design automation : New Orleans, Louisiana, USA; 10-14 June 2002 pp. 771 - 776
• Main Authors: Schrik, E., Meijs, N. P. van der
• Format: Conference Proceeding
• Language: English
• Published: New York, NY, USA ACM 10.06.2002
• Series: ACM Conferences
• Subjects: Applied sciences; Computing methodologies > Modeling and simulation > Model development and analysis; Computing methodologies > Modeling and simulation > Model development and analysis > Model verification and validation; Computing methodologies > Modeling and simulation > Model development and analysis > Modeling methodologies; Electronics; Exact sciences and technology; Hardware > Hardware validation > Functional verification; Integrated circuits; Integrated circuits by function (including memories and processors); Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; substrate noise; boundary element method; finite element method; modeling
• DOI: 10.1145/513918.514111
• ISBN: 1581134614; 9781581134612
• ISSN: 0738-100X

For present-day micro-electronic designs, it is becoming ever more important to accurately model substrate coupling effects. Basically, either a Finite Element Method (FEM) or a Boundary Element Method (BEM) can be used. The FEM is the most versatile and flexible whereas the BEM is faster, but requires a stratified, layout-independent doping profile for the substrate. Thus, the BEM is unable to properly model any specific, layout-dependent doping patterns that are usually present in the top layers of the substrate, such as channel stop layers. This paper describes a way to incorporate these doping patterns into our substrate model by combining a BEM for the stratified doping profiles with a 2D FEM for the top-level, layout-dependent doping patterns, thereby achieving improved flexibility compared to BEM and improved speed compared to FEM. The method has been implemented in the SPACE layout to circuit extractor and it has been successfully verified with two other tools.