Compiler-directed customization of ASIP cores

• Published in: International Conference on Hardware Software Codesign: Proceedings of the tenth international symposium on Hardware/software codesign; 06-08 May 2002 pp. 97 - 102
• Main Authors: Gupta, T. Vinod Kumar, Ko, Roberto E., Barua, Rajeev
• Format: Conference Proceeding
• Language: English
• Published: New York, NY, USA ACM 06.05.2002; IEEE
• Series: ACM Conferences
• Subjects: Application specific processors; Computer systems organization > Embedded and cyber-physical systems > Embedded systems; Costs; Educational institutions; Embedded system; Engineering profession; Hardware; Software and its engineering > Software notations and tools > Compilers; Software and its engineering > Software organization and properties > Software system structures > Embedded software; Software and its engineering > Software organization and properties > Software system structures > Real-time systems software; Technological innovation; soft cores; customization; embedded; ASIP
• ISBN: 1581135424; 9781581135428
• DOI: 10.1145/774789.774810

This paper presents an automatic method to customize embedded application-specific instruction processors (ASIPs) based on compiler analysis. ASIPs, also known as embedded soft cores, allow certain hardware parameters in the processor to be customized for a specific application domain. They offer low design cost as they use pre-designed and verified components. Our design goal is choosing parameter values for fastest runtime within a given silicon area budget for a particular application set. Present-day technologies for choosing parameter values rely on exhaustive simulation of the application set on all possible combinations of parameter values -- a time-consuming and non-scalable procedure. We propose a compiler-based method that automatically derives the optimal values of parameters without simulating any configuration. Further, we expand the space of parameters that can be changed from the limited set today, and evaluate the importance of each. Results show that for our benchmarks, the runtimes for different configurations are predicted with an average error of 2.5%. In the two area constrained customization problem we evaluate, our method is able to recommend the same configuration that is recommended by brute force exhaustive simulation.