New Generation of Predictive Technology Model for Sub-45nm Design Exploration

• Published in: 7th International Symposium on Quality Electronic Design (ISQED'06) pp. 585 - 590
• Main Authors: Zhao, Wei, Cao, Yu
• Format: Conference Proceeding
• Language: English
• Published: Washington, DC, USA IEEE Computer Society 27.03.2006; IEEE
• Series: ACM Conferences
• Subjects: Accuracy; Circuit synthesis; CMOS process; CMOS technology; Extrapolation; Hardware > Electronic design automation > Physical design (EDA); Hardware > Hardware validation; Hardware > Integrated circuits > Logic circuits; MOSFET circuits; Predictive models; Semiconductor device modeling; Silicon; Uncertainty
• ISBN: 9780769525235; 0769525237
• ISSN: 1948-3287; 1948-3295
• DOI: 10.1109/ISQED.2006.91

Predictive MOSFET model is critical for early circuit design research. To accurately predict the characteristics of nanoscale CMOS, emerging physical effects, such as process variations and physical correlations among model parameters, must be included. In addition, predictions across technology generations should be smooth to make continuous extrapolations. In this work, a new generation of Predictive Technology Model (PTM) is developed to accomplish these goals. Based on physical models and early stage silicon data, PTM of bulk CMOS for 130nm to 32nm technology nodes is successfully generated. By tuning ten parameters, PTM can be easily customized to cover a wide range of process uncertainties. The accuracy of PTM predictions is comprehensively verified: for NMOS, the error of Ion is 2% and for PMOS, it is 5%. Furthermore, the new PTM correctly captures process sensitivities in the nanometer regime. A webpage has been established for the release of PTM (http://www.eas.asu.edu/~ptm).