Fast scalable FPGA-based Network-on-Chip simulation models

• Published in: 2011 9th IEEE/ACM International Conference on Formal Methods and Models for Codesign pp. 77 - 82
• Main Author: Papamichael, M. K.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.07.2011
• Subjects: Buffer storage; Clocks; Delay; Engines; Field programmable gate arrays; FPGA; Memory management; Network; Network-on-Chip; Simulation; Software; Time-multiplexing; Virtualization
• ISBN: 9781457701177; 1457701170
• DOI: 10.1109/MEMCOD.2011.5970513

This paper presents a set of two FPGA-based Network-on-Chip (NoC) simulation engines that composed the winning design of the 2011 MEMOCODE Design Contest in the absolute performance class. Both simulation engines were developed in Bluespec System Verilog (BSV) and were implemented on a Xilinx ML605 FPGA development board. For smaller networks and simpler router configurations a direct-mapped approach was employed, where the network to be simulated was directly implemented on the FPGA. For larger networks, where a direct-mapped approach is not feasible due to FPGA resource limitations, a virtualized time-multiplexed approach was used. Compared to the provided software reference implementation, our direct-mapped approach achieves three orders of magnitude speedup, while our virtualized time-multiplexed approach achieves one to two orders of magnitude speedup, depending on the network and router configuration.