Symbolic RTL simulation

• Published in: Design Automation, 2001 Proceedings pp. 47 - 52
• Main Authors: Kölbl, Alferd, Kukula, James, Damiano, Robert
• Format: Conference Proceeding
• Language: English
• Published: New York, NY, USA ACM 01.01.2001; IEEE
• Series: ACM Conferences
• Subjects: Analytical models; Applied computing > Physical sciences and engineering > Electronics; Applied computing > Physical sciences and engineering > Engineering; Circuit simulation; Computational modeling; Delay; Electronic design automation and methodology; Formal verification; Hardware > Electronic design automation > High-level and register-transfer level synthesis; Hardware > Robustness; Hardware design languages; Permission; State-space methods; System testing
• ISBN: 1581132972; 9781581132977
• ISSN: 0738-100X
• DOI: 10.1145/378239.378278

Symbolic simulation is a promising formal verification technique combining the flexibility of conventional simulation with powerful symbolic methods. Unfortunately, existing symbolic simulators are restricted to gate level simulation or handle just a synthesizable subset of an HDL. Simulation of systems composed of design, testbench and correctness checkers, however, requires the complete set of HDL constructs. We present an approach that enables symbolic simulation of the complete set of RT-level Verilog constructs with full delay support. Additionally, we propose a flexible scheme for introducing symbolic variables and demonstrate how error traces can be simulated with this new scheme. Finally, we present some experimental results on an 8051 micro-controller design which prove the effectiveness of our approach.