Binary synthesis implementing external interrupt handler as independent module

• Published in: 2017 International Symposium on Rapid System Prototyping (RSP) pp. 92 - 98
• Main Authors: Ito, Naoya, Oosako, Yuuki, Ishiura, Nagisa, Kanbara, Hiroyuki, Tomiyama, Hiroyuki
• Format: Conference Proceeding
• Language: English
• Published: New York, NY, USA ACM 19.10.2017
• Series: ACM Conferences
• Subjects: Binary codes; binary synthesis; Computer systems organization > Embedded and cyber-physical systems > Embedded systems > Embedded hardware; Hardware; Hardware > Electronic design automation > High-level and register-transfer level synthesis > Hardware-software codesign; Hardware design languages; High-level synthesis; Indium tin oxide; interrupt handling; Registers; Software; Timing; high-level synthesis; interrupt handling; binary synthesis
• ISBN: 9781450354189; 1450354181
• ISSN: 2150-5519
• DOI: 10.1145/3130265.3130317

This article presents a method of synthesizing hardware from a given executable binary code with an external interrupt handler, where the normal flow and the interrupt handling are executed by separate hardware modules. Our previous method synthesized the whole program into a single hardware module, in which register save/restore imposed limitations on the timing to start interrupt handling and also impaired efficiency of the synthesized hardware. By executing the two tasks on separate modules, register save/restore can be eliminated, which allows interrupt handler to start at arbitrary timing and reduces the response time and cost of the hardware. By allowing two processes to run in parallel, total execution time is also reduced. An experiment with a simple program has shown that the execution cycles and the delay were reduced by about 80% and 20%, respectively, as compared with MIPS CPU. A motor controller driven by periodical interrupts from a timer has been successfully synthesized from C and assembly programs, which runs more than 20 times faster than the MIPS CPU.