Congestion-aware scheduling for NoC-based reconfigurable systems

• Published in: Proceedings of the Conference on Design, Automation and Test in Europe pp. 1561 - 1566
• Main Authors: Chao, Hung-Lin, Chen, Yean-Ru, Tung, Sheng-Ya, Hsiung, Pao-Ann, Chen, Sao-Jie
• Format: Conference Proceeding
• Language: English
• Published: San Jose, CA, USA EDA Consortium 12.03.2012
• Series: ACM Conferences
• Subjects: Hardware > Hardware validation; Hardware > Integrated circuits > Interconnect; Hardware > Very large scale integration design > Application-specific VLSI designs
• ISBN: 3981080181; 9783981080186
• DOI: 10.5555/2492708.2493089

Network-on-Chip (NoC) is becoming a promising communication architecture in place of dedicated interconnections and shared buses for embedded systems. Nevertheless, it has also created new design issue such as communication congestion and power consumption. A major factor leading to communication congestion is mapping of application tasks to NoC. Latency, throughput, and overall execution time are all affected by task mapping. As a solution, an efficient run-time Congestion-Aware Scheduling (CWS) is proposed for NoC-based reconfigurable systems, which predicts traffic pattern based on the link utilization. The proposed algorithm alleviates the overall congestion, instead of only improving the current packet blocking situation. Our experiment results have demonstrated that compared to other existing congestion-aware algorithm, the proposed CWS algorithm can reduce the average communication latency by 66%, increase the average throughput by 32%, reduce the energy consumption by 23%, and decrease the overall execution by 32%.